1. Field of the Invention
The present invention relates to an image reading device and an image forming device.
2. Description of the Related Art
An image reading device such as a scanner is a device that reads images for an original document as an analog image signal using a photoelectric converter, converts the analog signal to a digital signal, and outputs image data subjected to various processing. FIG. 14 is a schematic cross-sectional view of a typical image reading device.
The image reading device includes an exposure glass 2 on an upper surface of a scanner body 1 on which an original document 11 is placed. An optical scanning system including a first carriage 4 of a xenon lamp 3 that is an exposing unit that exposes original documents to light and a first reflecting mirror 4a, a second carriage 5 of a second reflecting mirror 5a, and a third reflecting mirror 5b, and a lens unit 6, is then provided within the scanner body 1 below the exposure glass 2.
The image reading device further includes a charge coupled device (CCD) linear image sensor (hereinafter, “CCD”) 8 that is a photoelectric converting unit mounted on a sensor board 7, and a signal processing unit 10 that processes read-in image signals inputted via a signal cable 9. A white reference plate 12 that corrects various distortion is also mounted on the front side of the exposure glass 2 at the upper surface of the scanner body 1.
When an original document is read by the image reading device, the first carriage 4 and the second carriage 5 of the optical scanning system are driven by a stepping motor so as to be moved in the direction of an arrow A of FIG. 1 in a sub scanning direction. The speed of movement of the second carriage 5 is ½ of the speed of movement of the first carriage 4. During the movement, the lower surface (image surface) of the original document 11 mounted on the exposure glass 2 is exposed to light by the xenon lamp 3 of the first carriage 4.
Light reflected by the lower surface of the original document 11 is then sequentially reflected and deflected by the first reflecting mirror 4a of the first carriage 4, and the second reflecting mirror 5a and the third reflecting mirror 5b of the second carriage 5 so as to be led to the lens unit 6. An image of the original document 11 is then reduced and formed on a light-receiving surface of the CCD 8 by the lens unit 6. The CCD 8 converts the image into an electrical signal in accordance with the light and shade (due to the intensity of the reflected light) of one line at a time using the period of the main scanning line period. An analog image signal is then outputted and is inputted from the sensor board 7 to the signal processing unit 10 via the signal cable 9.
Such the signal processing unit 10 of an image reading device of the conventional technology has been disclosed in Japanese Patent Application Laid-Open No. 2006-211042. As shown in FIG. 15, the signal processing unit 10 includes an analog signal processing unit 16 having a clamp circuit 17, a sample-hold circuit 18, an amplifier circuit 19, a multiplexer 20, an amplifier circuit 21, and an analog-to-digital (A/D) converter circuit 22, a latter stage shading correction circuit 23, a γ-correction circuit 24 and an interface (I/F) circuit 25. The signal processing unit 10 further includes an oscillator (OSC) 26 and a timing signal generating circuit 27 that controls operation timing of each part (circuit).
Control signal lines from the timing signal generating circuit 27 to each circuit section are indicated by solid-line arrows in FIG. 15. A control line for a microcomputer (abbreviated to “CPU”) included in a control unit (not shown) is depicted by hollow bold arrows.
An analog image signal Ve for even-numbered pixels and an analog image signal Vo for odd-numbered pixels are outputted from the CCD 8 in synchronization with a drive pulse, alternating-current(a.c.)—coupled by capacitors C, and inputted in the analog signal processing unit 16.
A black offset level of each analog image signal Ve and Vo is then clamped to a predetermined potential by the clamp circuit 17. The analog image signals Ve and Vo are then made into a continuous analog signal by the sample-hold circuit 18 by sampling and holding the signals using sample pulses. After the output of the image signals Ve and Vo for odd-numbered pixels and for even-numbered pixels is matched with a fixed level at the amplifier circuit 19, the signal is multiplexed at the multiplexer 20 and made into an analog image signal V.
The analog image signal V is then amplified to the level of a reference voltage for A/D conversion by the amplifier circuit 21 and converted into 8-bit digital data by the A/D converter circuit 22. A digital image signal obtained in the above manner is then corrected for sensitivity fluctuation and irregular light-distribution of the light-emitting system for the pixels of the CCD 8 at the shading correction circuit 23, and subjected to digital processing such as γ-correction by the γ-correction circuit 24.
Pulse signals and control signals used in the operation of the CCD 8 and other circuits are generated at the timing signal generating circuit 27 based on a clock pulse of the oscillator 26 and are provided to each circuit. The timing signal generating circuit 27 is controlled by a CPU of a control unit (not shown).
With the analog signal processing unit 16 of an image reading device of the conventional technology, the analog image signals Ve, Vo outputted by the CCD 8 are a.c.—coupled by the capacitors C. At the clamp circuit 17 (this circuit has two), control is then exerted so that a black level of the analog image signal Ve (Vo) is clamped to a predetermined offset potential (black offset level), as shown in FIGS. 16 and 17.
At the clamp circuit 17, as shown in the timing chart of FIGS. 18A and 18B, a clamp pulse is inputted at a black reference pixel region (where pixels exist but are optically masked) of the CCD output occurring at the main scanning line period (period of a line synchronization signal LSYNC, referred to simply as “line period”) of reading out image signals to one line from the CCD 8 using a CCD shift pulse. A clamp switch SW1 is then closed as shown in FIG. 17. The capacitor C is then charged so as to give a reference potential Vcc/2 that is a power supply voltage Vcc of the signal processing unit 10 divided by ½ by two resistors of the same resistance connected in series. After the clamp switch SW1 of the clamp circuit 17 is opened, the reference potential Vcc/2 and the offset analog image signal are inputted to the sample-hold circuit 18.
However, in the case of a circuit structure that a.c.—couples the analog image signal of the CCD 8 and carries out a clamping operation, when leakage current occurs between the a.c.—coupling capacitors C and the clamp circuit 17, a potential VL that is a reference for leakage and a leakage resistance RL exist virtually as shown in FIG. 16. A leakage current IL then flows at the capacitor C when the clamp switch SW1 is OFF and charging (or discharging) therefore takes place. When the clamp switch SW1 then goes ON as shown in FIG. 17, a current Isw flows due to charge charging up (or being discharged from) the capacitor C at the ON resistance of the clamp switch SW1. Therefore, a drop (or rise) in voltage occurs, and the offset potential of the image signal deviates from the clamp potential (Vcc/2).
At the sample-hold circuit 18 of the latter stage, the clamp potential (Vcc/2) is processed as a reference potential (black level). Offset deviation of the black level due to the magnitude of the leakage current can therefore no longer be ignored and deviation of this offset can be further amplified at the amplifier circuit 19 (FIG. 15) of the latter stage. A black offset correction circuit (not shown) is included within the analog signal processing unit 16 and has a correction range that is not so large but rather is normal. This means that correction cannot always be achieved depending on the extent of the offset deviation. The value of a digital image output for after quantization when offsets that cannot be corrected are taken as gray image data then becomes larger (or smaller), the density of the read image becomes lighter (or darker) than the actual density and this gives an abnormal image.
Leakage across wiring patterns of a printed wiring board (PWB) the circuit is mounted on, leakage of a.c.—coupling capacitors, and leakage occurring at the analog signal processing unit 16 (normally in the form of an integrated circuit) of the latter stage are given as causes of the occurrence of leakage current.
Deviation in the offset potential at the clamp circuit 17 depends on the ratio of the OFF period and the ON period of the clamp switch SW1. In the case of image reading devices having a number of line speeds depending on the reading mode, in the conventional art, the clamp period was fixed both in the case where the period is a long line period 1 as shown in FIG. 18A and in the case where the period is a short line period 2 as shown in FIG. 18B. The leakage current occurring due to the line period changing therefore changes and the offset potential changes.
The analog signal processing unit 16 tracks this change and ensures that adjustments are made by a black offset correction circuit (not shown) so as to attain a target black offset level even if the offset potential changes. However, when deviation of the offset potential due to changes in the line period is substantial, following this change becomes time-consuming and this influences the reading operation directly after changes in the line period.
Specific methods for black offset correction are as follows.
(1) A method that monitors output of a black reference pixel level after A/D conversion every main scanning line, provides feedback to input of a clamp circuit, and updates an offset correction value every line.
(2) A method of performing adjustment so that a black reference pixel level for after A/D conversion in an initialization operation when the power supply of the device is turned on becomes a desired value.
In the case of (1), the offset correction value is updated every line. However, rather than the whole of the difference between the target black offset level and the current offset level then being corrected in one line, some proportion of the difference is corrected in one line, with a target offset level then being converged upon over a number of lines. The reason for this is that attempting to follow in one line has the contrary effect of making it easier for noise to exert an influence.
When the line period then changes and the amount of the offset corrected by the black offset correction circuit changes, time corresponding to in the order of a number lines is required until this is dealt with.
In the case of (2), a correction value is obtained every line period when the power supply of the device goes ON, with the correction value changing every time the line period changes. Time is then required until the output level stabilizes after A/D conversion due to the response time of the circuit of the latter stage etc., although this is to a lesser extent than for (1).